1. Field of the Invention
The present invention relates to a semiconductor memory device such as a high integrated DRAM having a cell array divided into a plurality of cell blocks, wherein cell block selection is performed.
2. Description of the Related Art
In order to form a highly integrated DRAM, micro-patterning of elements and lines must be realized, and a cell array and a cell array drive circuit must be efficiently laid out within a predetermined chip area. In addition, the reading rate of cell data must be increased by decreasing a ratio C.sub.B /C.sub.S of the capacity C.sub.S of a memory cell to a capacity C.sub.B of bit lines. Furthermore, in order to reduce the power consumption due to charge/discharge of bit lines, the cell array must be divided into a plurality of cell blocks in the bit line direction. A highly integrated DRAM using a divided bit line and common Y-decoder method is inevitably required to satisfy these demands.
In order to realize this method, for example, a cell array is divided into four or eight cell blocks in the bit line direction. Bit lines in the respective cell blocks are independent of each other. A data I/O line shared by two cell blocks is arranged between two adjacent cell blocks. The bit lines in a selected one of the two adjacent cell blocks are connected to a data I/O line through a block selection gate and a column selection gate. A column selection signal line for controlling a column selection gate is continuously formed by a metal wire on the cell array constituted by the plurality of divided cell blocks, and a column selection signal as an output from a Y-decoder (i.e., column decoder) is supplied to the column selection signal line. A method of sharing at least part of a sense amplifier for bit line between adjacent cell blocks, i.e., a common sense amplifier method, is normally employed.
In a bit line precharge system of such a DRAM, it is known that an effective measure to reduce the power consumption and increase the speed of a bit line sense operation is to precharge bit lines at (1/2)Vcc.
A data I/O line, however, is preferably precharged to Vcc for the following reasons. First, assuming that the I/O line is precharged to the same potential as that of the bit lines, i.e., (1/2)Vcc, when a memory cell of a selected cell block is re-stored, an electric potential on bit line tends to be pulled up to an I/O line potential. A bit line sense amplifier is normally constituted by an NMOS sense amplifier and a PMOS sense amplifier. The NMOS sense amplifier is used to amplify a small signal. The PMOS sense amplifier is used to raise the potential of an "H"-level bit line to Vcc. For this reason, the drive power of the PMOS sense amplifier is not originally set to be large. Therefore, when a bit line is electrically connected to an I/O line potential, since the electric potential on bit line is pulled up to the I/O line, the PMOS sense amplifier cannot satisfactorily raise the "H"-level bit line potential to Vcc. This phenomenon becomes conspicuous especially when an I/O line has a large capacity, and abnormal operations may be caused. Second, if an I/O line can be precharged to Vcc, the initial sensing time of the I/O line of circuit of a bit line sense amplifier can be shortened.
The conventional DRAM of the divided bit line and common Y-decoder method, however, does not employ the precharge method, in which bit lines are precharged to (1/2)Vcc and an I/O lines are precharged to Vcc, for the following reason. Each column selection signal line is continuously arranged across a plurality of cell blocks and is connected to the column selection gates of the respective cell blocks. With this arrangement, when a given column selection signal is selected, the column selection gates of non-selected cell blocks which data should be not read out are opened. Subsequently, bit line sense amplifiers located outside the selection gates of the non-selected cell blocks and precharged to (1/2)Vcc are connected to I/O lines precharged to Vcc. As a result, the precharge potentials of the bit line sense amplifier is subjected to breakdown. The precharge method has not been employed for the above-described reason.
As described above, in the conventional DRAM of the divided bit line and common Y-decoder method, the precharge potential of each bit line cannot be set to be (1/2)Vcc and the precharge potential of each I/O line cannot be set to be Vcc. This interferes with realization of a further reduction in power consumption and an increase in operation speed.